URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_3/] [sim/] - Rev 344

Rev	Log message	Author	Age	Path
331	release 1.3	arniml	516d 23h	/t48/tags/rel_1_3/sim/
311	add t8042ah	arniml	530d 16h	/t48/trunk/sim/
306	add testbench for t8041 add test upi41/basic_echo	arniml	532d 16h	/t48/trunk/sim/
303	add prelim upi41 support	arniml	533d 17h	/t48/trunk/sim/
292	New directory structure.	root	5563d 03h	/t48/trunk/sim/
283	update to new mnemonic decoder	arniml	5877d 15h	/trunk/sim/
259	added t8243 core plus related testbenches	arniml	6533d 12h	/trunk/sim/
235	cleanup dependencies	arniml	6555d 12h	/trunk/sim/
232	update to new memory concept	arniml	6556d 12h	/trunk/sim/
223	obsoleted	arniml	6556d 12h	/trunk/sim/
218	simplifications	arniml	6643d 19h	/trunk/sim/
198	fix package dependencies	arniml	6787d 20h	/trunk/sim/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7120d 17h	/trunk/sim/
158	added hierarchies t8039_notri and t8048_notri	arniml	7120d 17h	/trunk/sim/
154	added t8039_notri hierarchy	arniml	7120d 17h	/trunk/sim/
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7122d 06h	/trunk/sim/
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7305d 16h	/trunk/sim/
112	update tb_behav_c0 for new ROM layout	arniml	7317d 01h	/trunk/sim/
93	add support for line coverage evaluation with gcov	arniml	7321d 21h	/trunk/sim/
84	add if_timing module	arniml	7342d 16h	/trunk/sim/