URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_3/] [sw/] [verif/] - Rev 245

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Rev	Log message	Author	Age	Path
245	initial check-in	arniml	6575d 00h	/t48/tags/rel_1_3/sw/verif/
239	adapt t48 external ROM offset	arniml	6592d 22h	/t48/tags/rel_1_3/sw/verif/
238	initial check-in	arniml	6592d 22h	/t48/tags/rel_1_3/sw/verif/
237	initial check-in	arniml	6592d 22h	/t48/tags/rel_1_3/sw/verif/
236	initial check-in	arniml	6592d 23h	/t48/tags/rel_1_3/sw/verif/
229	rework hex/simulation targets	arniml	6595d 22h	/t48/tags/rel_1_3/sw/verif/
199	initial check-in	arniml	6827d 02h	/t48/tags/rel_1_3/sw/verif/
194	initial check-in	arniml	6828d 13h	/t48/tags/rel_1_3/sw/verif/
185	initial check-in	arniml	6882d 01h	/t48/tags/rel_1_3/sw/verif/
184	initial check-in	arniml	6882d 03h	/t48/tags/rel_1_3/sw/verif/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6973d 04h	/t48/tags/rel_1_3/sw/verif/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7199d 03h	/t48/tags/rel_1_3/sw/verif/
131	update	arniml	7242d 22h	/t48/tags/rel_1_3/sw/verif/
130	initial check-in	arniml	7242d 22h	/t48/tags/rel_1_3/sw/verif/
125	exclude from dump compare	arniml	7312d 11h	/t48/tags/rel_1_3/sw/verif/
122	test MB after return from interrupt	arniml	7313d 08h	/t48/tags/rel_1_3/sw/verif/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7316d 02h	/t48/tags/rel_1_3/sw/verif/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7356d 12h	/t48/tags/rel_1_3/sw/verif/
102	update for changes in address space of external memory	arniml	7360d 08h	/t48/tags/rel_1_3/sw/verif/
99	initial check-in	arniml	7360d 08h	/t48/tags/rel_1_3/sw/verif/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_3/] [sw/] [verif/] - Rev 245

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