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[/] [t48/] [tags/] [rel_1_4/] - Rev 115

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Rev Log message Author Age Path
115 extend description arniml 7334d 15h /t48/tags/rel_1_4/
114 initial check-in arniml 7338d 11h /t48/tags/rel_1_4/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7344d 20h /t48/tags/rel_1_4/
112 update tb_behav_c0 for new ROM layout arniml 7344d 20h /t48/tags/rel_1_4/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7344d 20h /t48/tags/rel_1_4/
110 exchange syn_rom for lpm_rom arniml 7344d 20h /t48/tags/rel_1_4/
109 add new bug for release 0.1 BETA arniml 7345d 09h /t48/tags/rel_1_4/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7345d 09h /t48/tags/rel_1_4/
107 tie EA to '1' arniml 7345d 09h /t48/tags/rel_1_4/
106 clean-up use of ea_i arniml 7345d 09h /t48/tags/rel_1_4/
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7347d 19h /t48/tags/rel_1_4/
104 add white_box directory to test suite arniml 7348d 17h /t48/tags/rel_1_4/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7348d 17h /t48/tags/rel_1_4/
102 update for changes in address space of external memory arniml 7348d 17h /t48/tags/rel_1_4/
101 assert p2_read_p2_o when expander port is read arniml 7348d 17h /t48/tags/rel_1_4/
100 reorder data_o generation arniml 7348d 17h /t48/tags/rel_1_4/
99 initial check-in arniml 7348d 17h /t48/tags/rel_1_4/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7348d 17h /t48/tags/rel_1_4/
97 initial check-in arniml 7348d 17h /t48/tags/rel_1_4/
96 select dedicated directorie(s) for regression arniml 7349d 15h /t48/tags/rel_1_4/

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