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[/] [t48/] [tags/] [rel_1_4/] - Rev 131

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Rev Log message Author Age Path
131 update arniml 7272d 21h /t48/tags/rel_1_4/
130 initial check-in arniml 7272d 21h /t48/tags/rel_1_4/
129 cleanup copyright notice arniml 7335d 05h /t48/tags/rel_1_4/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered
arniml 7342d 09h /t48/tags/rel_1_4/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge
arniml 7342d 10h /t48/tags/rel_1_4/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell
arniml 7342d 10h /t48/tags/rel_1_4/
125 exclude from dump compare arniml 7342d 10h /t48/tags/rel_1_4/
124 fix wrong handling of MB after return from interrupt arniml 7343d 07h /t48/tags/rel_1_4/
123 support hex file for external ROM arniml 7343d 07h /t48/tags/rel_1_4/
122 test MB after return from interrupt arniml 7343d 07h /t48/tags/rel_1_4/
121 update bug description for
Program Memory bank can be switched during interrupt
arniml 7346d 00h /t48/tags/rel_1_4/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts
arniml 7346d 00h /t48/tags/rel_1_4/
119 add int_in_progress_o to entity of int module arniml 7346d 00h /t48/tags/rel_1_4/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7346d 00h /t48/tags/rel_1_4/
117 add bug
Program Memory bank can be switched during interrupt
arniml 7347d 01h /t48/tags/rel_1_4/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7375d 01h /t48/tags/rel_1_4/
115 extend description arniml 7376d 05h /t48/tags/rel_1_4/
114 initial check-in arniml 7380d 01h /t48/tags/rel_1_4/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7386d 10h /t48/tags/rel_1_4/
112 update tb_behav_c0 for new ROM layout arniml 7386d 10h /t48/tags/rel_1_4/

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