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[/] [t48/] [tags/] [rel_1_4/] - Rev 181

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Rev Log message Author Age Path
181 fix typo arniml 6950d 15h /t48/tags/rel_1_4/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6958d 21h /t48/tags/rel_1_4/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6958d 21h /t48/tags/rel_1_4/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6960d 09h /t48/tags/rel_1_4/
177 Implement db_dir_o glitch-safe arniml 6960d 09h /t48/tags/rel_1_4/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6960d 09h /t48/tags/rel_1_4/
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6961d 12h /t48/tags/rel_1_4/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6961d 12h /t48/tags/rel_1_4/
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6961d 12h /t48/tags/rel_1_4/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 6990d 09h /t48/tags/rel_1_4/
171 remove obsolete output stack_high_o arniml 6991d 09h /t48/tags/rel_1_4/
170 intermediate update arniml 6992d 15h /t48/tags/rel_1_4/
169 initial check-in arniml 6992d 21h /t48/tags/rel_1_4/
168 change address range of wb_master arniml 6992d 21h /t48/tags/rel_1_4/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 6992d 21h /t48/tags/rel_1_4/
166 assign default for state_s arniml 6994d 12h /t48/tags/rel_1_4/
165 add component wb_master.vhd arniml 6995d 11h /t48/tags/rel_1_4/
164 initial check-in arniml 6995d 12h /t48/tags/rel_1_4/
163 add bug
Wrong clock applied to T0		 arniml 6996d 11h /t48/tags/rel_1_4/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 6996d 11h /t48/tags/rel_1_4/

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