URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4/] - Rev 290

Rev	Log message	Author	Age	Path
290	remove obsolete components	arniml	5979d 20h	/t48/tags/rel_1_4/
288	updates for release 1.1	arniml	5980d 16h	/t48/tags/rel_1_4/
287	add notes on FPGA implementation	arniml	5980d 17h	/t48/tags/rel_1_4/
286	hierarchy update, RAM and ROM clarification	arniml	5980d 17h	/t48/tags/rel_1_4/
285	generate D for synchronous implementation in clocked process	arniml	5981d 18h	/t48/tags/rel_1_4/
284	better support for ISE/XST: opc_table and opc_decoder merged into decoder_pack and decoder	arniml	5981d 18h	/t48/tags/rel_1_4/
283	update to new mnemonic decoder	arniml	5981d 18h	/t48/tags/rel_1_4/
282	decouple bidir port T0 from P1 fixes testcase black_box/tx/t0	arniml	5982d 17h	/t48/tags/rel_1_4/
281	clarify testcase compilation	arniml	5982d 17h	/t48/tags/rel_1_4/
280	added syn directory structure	arniml	5983d 17h	/t48/tags/rel_1_4/
279	update	arniml	5998d 15h	/t48/tags/rel_1_4/
278	initial check-in	arniml	5998d 18h	/t48/tags/rel_1_4/
276	add change notes for release 1.0	arniml	6479d 16h	/t48/tags/rel_1_4/
275	fix sensitivity list	arniml	6480d 14h	/t48/tags/rel_1_4/
274	revision 1.0	arniml	6480d 14h	/t48/tags/rel_1_4/
273	reset counter_q	arniml	6498d 01h	/t48/tags/rel_1_4/
272	fix entity port names	arniml	6502d 02h	/t48/tags/rel_1_4/
271	initial check-in	arniml	6502d 02h	/t48/tags/rel_1_4/
270	fix component name	arniml	6502d 03h	/t48/tags/rel_1_4/
269	update list for inclusion of t8243 testbenches	arniml	6629d 16h	/t48/tags/rel_1_4/