URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4/] - Rev 87

Rev	Log message	Author	Age	Path
87	abort gracfullt if memory bank switching does not work	arniml	7406d 15h	/t48/tags/rel_1_4/
86	update notice about expander port instructions	arniml	7406d 21h	/t48/tags/rel_1_4/
85	initial check-in	arniml	7406d 21h	/t48/tags/rel_1_4/
84	add if_timing module	arniml	7412d 12h	/t48/tags/rel_1_4/
83	connect if_timing to P2 output of T48	arniml	7412d 12h	/t48/tags/rel_1_4/
82	check expander timings	arniml	7412d 12h	/t48/tags/rel_1_4/
81	initial check-in	arniml	7412d 16h	/t48/tags/rel_1_4/
80	added if_timing	arniml	7412d 16h	/t48/tags/rel_1_4/
79	add if_timing module	arniml	7412d 16h	/t48/tags/rel_1_4/
78	adjust external timing of BUS	arniml	7412d 16h	/t48/tags/rel_1_4/
77	move from std_logic_arith to numeric_std	arniml	7413d 09h	/t48/tags/rel_1_4/
76	initial check-in	arniml	7413d 13h	/t48/tags/rel_1_4/
75	remove obsolete design unit	arniml	7413d 13h	/t48/tags/rel_1_4/
74	enhance pass/fail detection	arniml	7413d 21h	/t48/tags/rel_1_4/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7413d 21h	/t48/tags/rel_1_4/
72	removed superfluous signal from sensitivity list	arniml	7413d 21h	/t48/tags/rel_1_4/
71	add T8039 and its testbench	arniml	7419d 13h	/t48/tags/rel_1_4/
70	clean test cell before make	arniml	7419d 13h	/t48/tags/rel_1_4/
69	fix name of istrobe	arniml	7419d 13h	/t48/tags/rel_1_4/
68	connect T0 and T1 to P1	arniml	7419d 13h	/t48/tags/rel_1_4/