URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 116

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Rev	Log message	Author	Age	Path
116	Changed the module instantiation into the dot form.	creep	5587d 10h	/t6507lp/
115	Renamed the signal control. It is mem_rw now.	creep	5587d 10h	/t6507lp/
114	Created a global timescale file for the project. Added to the top module.	creep	5587d 11h	/t6507lp/
113	Timescale was unified.	gabrieloshiro	5587d 11h	/t6507lp/
112	Created a global timescale file for the project.	creep	5587d 11h	/t6507lp/
111	Performed some linting after coding was finished.	creep	5588d 02h	/t6507lp/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5588d 03h	/t6507lp/
109	PLA and PLP are coded and simulated.	creep	5588d 06h	/t6507lp/
108	PHA and PHP are coded and simulated.	creep	5588d 07h	/t6507lp/
107	The RTS instruction is working fine. Coded and simulated.	creep	5588d 08h	/t6507lp/
106	First stable version. Things seems to be working. Simulation is currently at 20%.	gabrieloshiro	5588d 08h	/t6507lp/
105	The RTI instruction is working fine. Coded and simulated.	creep	5588d 08h	/t6507lp/
104	The BRK instruction is working. The reset vector was tested also.	creep	5588d 10h	/t6507lp/
103	Some early modifications to support the special stack instructions.	creep	5589d 03h	/t6507lp/
102	Some early modifications to support the special stack instructions.	creep	5589d 06h	/t6507lp/
101	Absolute indirect addressing mode is coded and simulated.	creep	5589d 10h	/t6507lp/
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5589d 11h	/t6507lp/
99	Only Package.v should be used.	creep	5589d 11h	/t6507lp/
98	Updated status and some comments.	creep	5589d 11h	/t6507lp/
97	Removed obsolete TODO.	creep	5589d 11h	/t6507lp/

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Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 116

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