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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 120

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Rev Log message Author Age Path
120 Added some extra commentaries. creep 5591d 23h /t6507lp/
119 removing old file. creep 5592d 02h /t6507lp/
118 The top level name was in uppercase. The correct is lowercase. creep 5592d 03h /t6507lp/
117 Fixed the top level and connected the entire project. creep 5592d 03h /t6507lp/
116 Changed the module instantiation into the dot form. creep 5592d 04h /t6507lp/
115 Renamed the signal control. It is mem_rw now. creep 5592d 04h /t6507lp/
114 Created a global timescale file for the project. Added to the top module. creep 5592d 04h /t6507lp/
113 Timescale was unified. gabrieloshiro 5592d 04h /t6507lp/
112 Created a global timescale file for the project. creep 5592d 04h /t6507lp/
111 Performed some linting after coding was finished. creep 5592d 20h /t6507lp/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5592d 21h /t6507lp/
109 PLA and PLP are coded and simulated. creep 5593d 00h /t6507lp/
108 PHA and PHP are coded and simulated. creep 5593d 00h /t6507lp/
107 The RTS instruction is working fine. Coded and simulated. creep 5593d 01h /t6507lp/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5593d 01h /t6507lp/
105 The RTI instruction is working fine. Coded and simulated. creep 5593d 02h /t6507lp/
104 The BRK instruction is working. The reset vector was tested also. creep 5593d 03h /t6507lp/
103 Some early modifications to support the special stack instructions. creep 5593d 21h /t6507lp/
102 Some early modifications to support the special stack instructions. creep 5594d 00h /t6507lp/
101 Absolute indirect addressing mode is coded and simulated. creep 5594d 03h /t6507lp/

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