URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 127

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5622d 15h	/t6507lp/
126	Added a wrapper for the ALU. This file creates the clock for Specman.	creep	5622d 16h	/t6507lp/
125	All files are linked to each other. RTL is still not linked through hdl_path()	creep	5623d 08h	/t6507lp/
124	All signals are mapped on the BFM and MON using the SIG_MAP.	creep	5623d 10h	/t6507lp/
123	Added all the eRM files.	creep	5623d 10h	/t6507lp/
122	Adding alu_mon.e	creep	5623d 11h	/t6507lp/
121	Adding formal verification folder.	creep	5623d 11h	/t6507lp/
120	Added some extra commentaries.	creep	5624d 11h	/t6507lp/
119	removing old file.	creep	5624d 14h	/t6507lp/
118	The top level name was in uppercase. The correct is lowercase.	creep	5624d 15h	/t6507lp/
117	Fixed the top level and connected the entire project.	creep	5624d 15h	/t6507lp/
116	Changed the module instantiation into the dot form.	creep	5624d 16h	/t6507lp/
115	Renamed the signal control. It is mem_rw now.	creep	5624d 16h	/t6507lp/
114	Created a global timescale file for the project. Added to the top module.	creep	5624d 16h	/t6507lp/
113	Timescale was unified.	gabrieloshiro	5624d 16h	/t6507lp/
112	Created a global timescale file for the project.	creep	5624d 16h	/t6507lp/
111	Performed some linting after coding was finished.	creep	5625d 08h	/t6507lp/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5625d 09h	/t6507lp/
109	PLA and PLP are coded and simulated.	creep	5625d 11h	/t6507lp/
108	PHA and PHP are coded and simulated.	creep	5625d 12h	/t6507lp/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 127

Filtering Options