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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 129

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129 RTL and e files are truly linked now. Some very early coverage is done. creep 5589d 17h /t6507lp/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5589d 21h /t6507lp/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5589d 22h /t6507lp/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5589d 23h /t6507lp/
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5590d 15h /t6507lp/
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5590d 17h /t6507lp/
123 Added all the eRM files. creep 5590d 17h /t6507lp/
122 Adding alu_mon.e creep 5590d 18h /t6507lp/
121 Adding formal verification folder. creep 5590d 18h /t6507lp/
120 Added some extra commentaries. creep 5591d 18h /t6507lp/
119 removing old file. creep 5591d 21h /t6507lp/
118 The top level name was in uppercase. The correct is lowercase. creep 5591d 22h /t6507lp/
117 Fixed the top level and connected the entire project. creep 5591d 22h /t6507lp/
116 Changed the module instantiation into the dot form. creep 5591d 23h /t6507lp/
115 Renamed the signal control. It is mem_rw now. creep 5591d 23h /t6507lp/
114 Created a global timescale file for the project. Added to the top module. creep 5591d 23h /t6507lp/
113 Timescale was unified. gabrieloshiro 5591d 23h /t6507lp/
112 Created a global timescale file for the project. creep 5591d 23h /t6507lp/
111 Performed some linting after coding was finished. creep 5592d 15h /t6507lp/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5592d 16h /t6507lp/

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