OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 133

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
133 Checker updated. ADD's and AND's should be working fine. creep 5616d 09h /t6507lp/
132 Added a .e file containing the opcodes. Other files modified as well. Chebeing written. creep 5616d 10h /t6507lp/
131 Added a checker for i/o comparison. creep 5619d 06h /t6507lp/
130 Added alu_input.e to the repository. creep 5619d 09h /t6507lp/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5619d 09h /t6507lp/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5619d 13h /t6507lp/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5619d 14h /t6507lp/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5619d 14h /t6507lp/
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5620d 06h /t6507lp/
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5620d 08h /t6507lp/
123 Added all the eRM files. creep 5620d 09h /t6507lp/
122 Adding alu_mon.e creep 5620d 09h /t6507lp/
121 Adding formal verification folder. creep 5620d 09h /t6507lp/
120 Added some extra commentaries. creep 5621d 09h /t6507lp/
119 removing old file. creep 5621d 12h /t6507lp/
118 The top level name was in uppercase. The correct is lowercase. creep 5621d 13h /t6507lp/
117 Fixed the top level and connected the entire project. creep 5621d 13h /t6507lp/
116 Changed the module instantiation into the dot form. creep 5621d 14h /t6507lp/
115 Renamed the signal control. It is mem_rw now. creep 5621d 14h /t6507lp/
114 Created a global timescale file for the project. Added to the top module. creep 5621d 14h /t6507lp/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.