URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 76

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5656d 20h	/t6507lp/
75	First working version!	gabrieloshiro	5656d 20h	/t6507lp/
74	The file now describes who is doing what.	creep	5656d 20h	/t6507lp/
73	Added schedule file into the readme file.	creep	5656d 20h	/t6507lp/
72	Project management folder.	creep	5656d 20h	/t6507lp/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5656d 21h	/t6507lp/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5660d 17h	/t6507lp/
69	Added signal origin/destination.	creep	5660d 19h	/t6507lp/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5660d 19h	/t6507lp/
67	File name change to lowercase. HAL says so!	creep	5660d 21h	/t6507lp/
66	File name change to lowercase. HAL says so!	creep	5660d 21h	/t6507lp/
65	Now the blocks are connected.	gabrieloshiro	5661d 16h	/t6507lp/
64	Constant were wrong.	gabrieloshiro	5661d 16h	/t6507lp/
63	Fixed several HAL warnings. Still plenty to do.	creep	5661d 16h	/t6507lp/
62	The DUT file name changed.	creep	5661d 16h	/t6507lp/
61	File name change to lowercase. HAL says so!	creep	5661d 17h	/t6507lp/
60	File name change. HAL says so!	creep	5661d 17h	/t6507lp/
59	I`ve fixed some latch creation.	gabrieloshiro	5661d 17h	/t6507lp/
58	ALU with all opcodes ready for simulation.	gabrieloshiro	5661d 18h	/t6507lp/
57	A very simple testbench that checks the execution for a single instruction, i.e. no memory.	creep	5661d 18h	/t6507lp/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 76

Filtering Options