URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] - Rev 262

Rev	Log message	Author	Age	Path
262	Final synthesis script.	creep	5557d 15h	/t6507lp/trunk/
261	Added a better clock gating scheme with enable sharing	creep	5557d 17h	/t6507lp/trunk/
260	removing useless files	creep	5560d 12h	/t6507lp/trunk/
259	sync	creep	5560d 12h	/t6507lp/trunk/
258	Fixed the input parametric testing logic, removed a pad.	creep	5560d 12h	/t6507lp/trunk/
257	Modified script for DFT	creep	5582d 15h	/t6507lp/trunk/
256	fp files	creep	5582d 15h	/t6507lp/trunk/
255	Changed the PADS verilog description to minimize violations	creep	5582d 15h	/t6507lp/trunk/
254	Fixed a latch in the design	creep	5582d 15h	/t6507lp/trunk/
253	Changed the rw_mem signal name in the hierarchy	creep	5605d 15h	/t6507lp/trunk/
252	Added a stubs file for the pads.	creep	5605d 16h	/t6507lp/trunk/
251	Added the io wrapper	creep	5605d 18h	/t6507lp/trunk/
250	Synthesis script changed	creep	5605d 19h	/t6507lp/trunk/
249	Renamed the synthesis script	creep	5606d 15h	/t6507lp/trunk/
248	Added a low power synthesis script	creep	5611d 13h	/t6507lp/trunk/
247	Added the cpu mapped verilog	creep	5611d 13h	/t6507lp/trunk/
246	Added some older files plus the first syn script	creep	5612d 18h	/t6507lp/trunk/
245	Added a few dirs for the synthesis	creep	5612d 18h	/t6507lp/trunk/
244	Added a few dirs for the synthesis	creep	5612d 18h	/t6507lp/trunk/
243	Fixing STA_IDY bug	creep	5654d 11h	/t6507lp/trunk/