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[/] [t6507lp/] [trunk/] [rtl/] - Rev 124

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Rev Log message Author Age Path
120 Added some extra commentaries. creep 5630d 21h /t6507lp/trunk/rtl/
119 removing old file. creep 5630d 23h /t6507lp/trunk/rtl/
118 The top level name was in uppercase. The correct is lowercase. creep 5631d 01h /t6507lp/trunk/rtl/
117 Fixed the top level and connected the entire project. creep 5631d 01h /t6507lp/trunk/rtl/
116 Changed the module instantiation into the dot form. creep 5631d 01h /t6507lp/trunk/rtl/
115 Renamed the signal control. It is mem_rw now. creep 5631d 01h /t6507lp/trunk/rtl/
114 Created a global timescale file for the project. Added to the top module. creep 5631d 02h /t6507lp/trunk/rtl/
113 Timescale was unified. gabrieloshiro 5631d 02h /t6507lp/trunk/rtl/
112 Created a global timescale file for the project. creep 5631d 02h /t6507lp/trunk/rtl/
111 Performed some linting after coding was finished. creep 5631d 17h /t6507lp/trunk/rtl/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5631d 18h /t6507lp/trunk/rtl/
109 PLA and PLP are coded and simulated. creep 5631d 21h /t6507lp/trunk/rtl/
108 PHA and PHP are coded and simulated. creep 5631d 22h /t6507lp/trunk/rtl/
107 The RTS instruction is working fine. Coded and simulated. creep 5631d 23h /t6507lp/trunk/rtl/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5631d 23h /t6507lp/trunk/rtl/
105 The RTI instruction is working fine. Coded and simulated. creep 5631d 23h /t6507lp/trunk/rtl/
104 The BRK instruction is working. The reset vector was tested also. creep 5632d 01h /t6507lp/trunk/rtl/
103 Some early modifications to support the special stack instructions. creep 5632d 19h /t6507lp/trunk/rtl/
102 Some early modifications to support the special stack instructions. creep 5632d 21h /t6507lp/trunk/rtl/
101 Absolute indirect addressing mode is coded and simulated. creep 5633d 01h /t6507lp/trunk/rtl/

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