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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 115

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Rev Log message Author Age Path
115 Renamed the signal control. It is mem_rw now. creep 5632d 13h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5632d 14h /t6507lp/trunk/rtl/verilog/
113 Timescale was unified. gabrieloshiro 5632d 14h /t6507lp/trunk/rtl/verilog/
112 Created a global timescale file for the project. creep 5632d 14h /t6507lp/trunk/rtl/verilog/
111 Performed some linting after coding was finished. creep 5633d 05h /t6507lp/trunk/rtl/verilog/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5633d 06h /t6507lp/trunk/rtl/verilog/
109 PLA and PLP are coded and simulated. creep 5633d 09h /t6507lp/trunk/rtl/verilog/
108 PHA and PHP are coded and simulated. creep 5633d 10h /t6507lp/trunk/rtl/verilog/
107 The RTS instruction is working fine. Coded and simulated. creep 5633d 11h /t6507lp/trunk/rtl/verilog/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5633d 11h /t6507lp/trunk/rtl/verilog/
105 The RTI instruction is working fine. Coded and simulated. creep 5633d 11h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 5633d 13h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 5634d 06h /t6507lp/trunk/rtl/verilog/
102 Some early modifications to support the special stack instructions. creep 5634d 09h /t6507lp/trunk/rtl/verilog/
101 Absolute indirect addressing mode is coded and simulated. creep 5634d 13h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5634d 14h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 5634d 14h /t6507lp/trunk/rtl/verilog/
98 Updated status and some comments. creep 5634d 14h /t6507lp/trunk/rtl/verilog/
97 Removed obsolete TODO. creep 5634d 14h /t6507lp/trunk/rtl/verilog/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5637d 06h /t6507lp/trunk/rtl/verilog/

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