OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 116

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 Changed the module instantiation into the dot form. creep 5579d 04h /t6507lp/trunk/rtl/verilog/
115 Renamed the signal control. It is mem_rw now. creep 5579d 04h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5579d 04h /t6507lp/trunk/rtl/verilog/
113 Timescale was unified. gabrieloshiro 5579d 04h /t6507lp/trunk/rtl/verilog/
112 Created a global timescale file for the project. creep 5579d 04h /t6507lp/trunk/rtl/verilog/
111 Performed some linting after coding was finished. creep 5579d 20h /t6507lp/trunk/rtl/verilog/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5579d 21h /t6507lp/trunk/rtl/verilog/
109 PLA and PLP are coded and simulated. creep 5580d 00h /t6507lp/trunk/rtl/verilog/
108 PHA and PHP are coded and simulated. creep 5580d 00h /t6507lp/trunk/rtl/verilog/
107 The RTS instruction is working fine. Coded and simulated. creep 5580d 01h /t6507lp/trunk/rtl/verilog/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5580d 01h /t6507lp/trunk/rtl/verilog/
105 The RTI instruction is working fine. Coded and simulated. creep 5580d 01h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 5580d 03h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 5580d 21h /t6507lp/trunk/rtl/verilog/
102 Some early modifications to support the special stack instructions. creep 5581d 00h /t6507lp/trunk/rtl/verilog/
101 Absolute indirect addressing mode is coded and simulated. creep 5581d 03h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5581d 04h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 5581d 05h /t6507lp/trunk/rtl/verilog/
98 Updated status and some comments. creep 5581d 05h /t6507lp/trunk/rtl/verilog/
97 Removed obsolete TODO. creep 5581d 05h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.