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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 127

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Rev Log message Author Age Path
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5592d 03h /t6507lp/trunk/rtl/verilog/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5592d 04h /t6507lp/trunk/rtl/verilog/
120 Added some extra commentaries. creep 5593d 23h /t6507lp/trunk/rtl/verilog/
119 removing old file. creep 5594d 02h /t6507lp/trunk/rtl/verilog/
118 The top level name was in uppercase. The correct is lowercase. creep 5594d 03h /t6507lp/trunk/rtl/verilog/
117 Fixed the top level and connected the entire project. creep 5594d 03h /t6507lp/trunk/rtl/verilog/
116 Changed the module instantiation into the dot form. creep 5594d 03h /t6507lp/trunk/rtl/verilog/
115 Renamed the signal control. It is mem_rw now. creep 5594d 04h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5594d 04h /t6507lp/trunk/rtl/verilog/
113 Timescale was unified. gabrieloshiro 5594d 04h /t6507lp/trunk/rtl/verilog/
112 Created a global timescale file for the project. creep 5594d 04h /t6507lp/trunk/rtl/verilog/
111 Performed some linting after coding was finished. creep 5594d 19h /t6507lp/trunk/rtl/verilog/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5594d 21h /t6507lp/trunk/rtl/verilog/
109 PLA and PLP are coded and simulated. creep 5594d 23h /t6507lp/trunk/rtl/verilog/
108 PHA and PHP are coded and simulated. creep 5595d 00h /t6507lp/trunk/rtl/verilog/
107 The RTS instruction is working fine. Coded and simulated. creep 5595d 01h /t6507lp/trunk/rtl/verilog/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5595d 01h /t6507lp/trunk/rtl/verilog/
105 The RTI instruction is working fine. Coded and simulated. creep 5595d 01h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 5595d 03h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 5595d 21h /t6507lp/trunk/rtl/verilog/

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