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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 141

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Rev Log message Author Age Path
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5616d 21h /t6507lp/trunk/rtl/verilog/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5616d 21h /t6507lp/trunk/rtl/verilog/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5616d 21h /t6507lp/trunk/rtl/verilog/
136 Some minor coding style changes. gabrieloshiro 5617d 17h /t6507lp/trunk/rtl/verilog/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5621d 16h /t6507lp/trunk/rtl/verilog/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5621d 20h /t6507lp/trunk/rtl/verilog/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5621d 21h /t6507lp/trunk/rtl/verilog/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5621d 21h /t6507lp/trunk/rtl/verilog/
120 Added some extra commentaries. creep 5623d 16h /t6507lp/trunk/rtl/verilog/
119 removing old file. creep 5623d 19h /t6507lp/trunk/rtl/verilog/
118 The top level name was in uppercase. The correct is lowercase. creep 5623d 21h /t6507lp/trunk/rtl/verilog/
117 Fixed the top level and connected the entire project. creep 5623d 21h /t6507lp/trunk/rtl/verilog/
116 Changed the module instantiation into the dot form. creep 5623d 21h /t6507lp/trunk/rtl/verilog/
115 Renamed the signal control. It is mem_rw now. creep 5623d 21h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5623d 21h /t6507lp/trunk/rtl/verilog/
113 Timescale was unified. gabrieloshiro 5623d 22h /t6507lp/trunk/rtl/verilog/
112 Created a global timescale file for the project. creep 5623d 22h /t6507lp/trunk/rtl/verilog/
111 Performed some linting after coding was finished. creep 5624d 13h /t6507lp/trunk/rtl/verilog/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5624d 14h /t6507lp/trunk/rtl/verilog/
109 PLA and PLP are coded and simulated. creep 5624d 17h /t6507lp/trunk/rtl/verilog/

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