OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 152

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
152 Bug #24 from trac was fixed. gabrieloshiro 5616d 04h /t6507lp/trunk/rtl/verilog/
151 tah comitado! gabrieloshiro 5616d 05h /t6507lp/trunk/rtl/verilog/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5616d 05h /t6507lp/trunk/rtl/verilog/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5616d 05h /t6507lp/trunk/rtl/verilog/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5616d 06h /t6507lp/trunk/rtl/verilog/
146 Fixed ticket #13: reset behavior in the FSM. creep 5617d 02h /t6507lp/trunk/rtl/verilog/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5617d 04h /t6507lp/trunk/rtl/verilog/
144 Checker is working fine. Hunting bugs... creep 5617d 05h /t6507lp/trunk/rtl/verilog/
143 Modified the inputs so the alu resets. creep 5617d 06h /t6507lp/trunk/rtl/verilog/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5617d 08h /t6507lp/trunk/rtl/verilog/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5617d 09h /t6507lp/trunk/rtl/verilog/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5617d 09h /t6507lp/trunk/rtl/verilog/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5617d 09h /t6507lp/trunk/rtl/verilog/
136 Some minor coding style changes. gabrieloshiro 5618d 05h /t6507lp/trunk/rtl/verilog/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5622d 04h /t6507lp/trunk/rtl/verilog/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5622d 08h /t6507lp/trunk/rtl/verilog/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5622d 09h /t6507lp/trunk/rtl/verilog/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5622d 09h /t6507lp/trunk/rtl/verilog/
120 Added some extra commentaries. creep 5624d 05h /t6507lp/trunk/rtl/verilog/
119 removing old file. creep 5624d 07h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.