OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 156

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5584d 16h /t6507lp/trunk/rtl/verilog/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5584d 20h /t6507lp/trunk/rtl/verilog/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 5585d 14h /t6507lp/trunk/rtl/verilog/
152 Bug #24 from trac was fixed. gabrieloshiro 5585d 14h /t6507lp/trunk/rtl/verilog/
151 tah comitado! gabrieloshiro 5585d 15h /t6507lp/trunk/rtl/verilog/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5585d 15h /t6507lp/trunk/rtl/verilog/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5585d 16h /t6507lp/trunk/rtl/verilog/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5585d 16h /t6507lp/trunk/rtl/verilog/
146 Fixed ticket #13: reset behavior in the FSM. creep 5586d 12h /t6507lp/trunk/rtl/verilog/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5586d 15h /t6507lp/trunk/rtl/verilog/
144 Checker is working fine. Hunting bugs... creep 5586d 15h /t6507lp/trunk/rtl/verilog/
143 Modified the inputs so the alu resets. creep 5586d 16h /t6507lp/trunk/rtl/verilog/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5586d 18h /t6507lp/trunk/rtl/verilog/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5586d 19h /t6507lp/trunk/rtl/verilog/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5586d 19h /t6507lp/trunk/rtl/verilog/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5586d 19h /t6507lp/trunk/rtl/verilog/
136 Some minor coding style changes. gabrieloshiro 5587d 15h /t6507lp/trunk/rtl/verilog/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5591d 14h /t6507lp/trunk/rtl/verilog/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5591d 18h /t6507lp/trunk/rtl/verilog/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5591d 19h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.