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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 198

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Rev Log message Author Age Path
198 Removed the old I/O file creep 5602d 02h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5602d 02h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5602d 19h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5602d 23h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5603d 01h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5603d 21h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5603d 22h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5609d 02h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5609d 02h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5609d 19h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5609d 19h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5609d 19h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5616d 18h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5617d 02h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 5617d 19h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5617d 22h /t6507lp/trunk/rtl/verilog/
179 STA, STY and STX fixed gabrieloshiro 5618d 00h /t6507lp/trunk/rtl/verilog/
178 STA, STY and STX fixed gabrieloshiro 5618d 00h /t6507lp/trunk/rtl/verilog/
176 RTI works for me gabrieloshiro 5618d 03h /t6507lp/trunk/rtl/verilog/
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5618d 23h /t6507lp/trunk/rtl/verilog/

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