OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 208

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5565d 06h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5565d 08h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5565d 12h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5568d 06h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5568d 07h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 5568d 09h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 5568d 10h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 5568d 12h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5568d 12h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5569d 05h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5569d 09h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5569d 12h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5570d 07h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5570d 08h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5575d 12h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5575d 12h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5576d 05h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5576d 05h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5576d 05h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5583d 04h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.