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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 209

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Rev Log message Author Age Path
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5545d 13h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5545d 15h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5545d 19h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5548d 13h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5548d 14h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 5548d 17h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 5548d 17h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 5548d 19h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5548d 19h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5549d 13h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5549d 16h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5549d 19h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5550d 14h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5550d 15h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5555d 19h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5555d 19h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5556d 12h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5556d 12h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5556d 12h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5563d 11h /t6507lp/trunk/rtl/verilog/

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