URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 242

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Rev	Log message	Author	Age	Path
242	Bug regardind the STA_IDY opcode	creep	5550d 16h	/t6507lp/trunk/rtl/verilog/
239	Zero flag fixed for SBC while in Decimal Mode. Bug #34.	gabrieloshiro	5551d 18h	/t6507lp/trunk/rtl/verilog/
238	ALU file is linted.	creep	5554d 15h	/t6507lp/trunk/rtl/verilog/
237	Added a preliminary collision detection logic.	creep	5555d 16h	/t6507lp/trunk/rtl/verilog/
236	Added the video converter testbench to the repository.	creep	5555d 20h	/t6507lp/trunk/rtl/verilog/
235	Bug #60: added a brief simulation to the video_converter module.	creep	5556d 13h	/t6507lp/trunk/rtl/verilog/
234	SBC Decimal mode 100% verified.	creep	5561d 15h	/t6507lp/trunk/rtl/verilog/
233	ADC and SBC are 100% verified in regular mode. Decimal mode still missing.	creep	5561d 19h	/t6507lp/trunk/rtl/verilog/
232	New video test.	creep	5563d 13h	/t6507lp/trunk/rtl/verilog/
231	Minor bugs fixed.	gabrieloshiro	5563d 15h	/t6507lp/trunk/rtl/verilog/
230	Changed TIA behavior. It is now pixel-based.	creep	5563d 15h	/t6507lp/trunk/rtl/verilog/
229	Created a one-line pattern.	creep	5563d 19h	/t6507lp/trunk/rtl/verilog/
228		gabrieloshiro	5563d 20h	/t6507lp/trunk/rtl/verilog/
227	Fixing conflicts.	creep	5563d 20h	/t6507lp/trunk/rtl/verilog/
226	work plz	creep	5563d 20h	/t6507lp/trunk/rtl/verilog/
225	Minor changes!	gabrieloshiro	5564d 12h	/t6507lp/trunk/rtl/verilog/
224	Added a top level for the tests.	creep	5564d 14h	/t6507lp/trunk/rtl/verilog/
223	Minor sintax errors fixed.	gabrieloshiro	5564d 14h	/t6507lp/trunk/rtl/verilog/
222	Added a simple line-by-line tester.	creep	5564d 16h	/t6507lp/trunk/rtl/verilog/
221	Added a VGA controller.	creep	5564d 19h	/t6507lp/trunk/rtl/verilog/

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 242

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