URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 249

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Rev	Log message	Author	Age	Path
246	Added some older files plus the first syn script	creep	5613d 08h	/t6507lp/trunk/rtl/verilog/
243	Fixing STA_IDY bug	creep	5655d 01h	/t6507lp/trunk/rtl/verilog/
242	Bug regardind the STA_IDY opcode	creep	5655d 05h	/t6507lp/trunk/rtl/verilog/
239	Zero flag fixed for SBC while in Decimal Mode. Bug #34.	gabrieloshiro	5656d 07h	/t6507lp/trunk/rtl/verilog/
238	ALU file is linted.	creep	5659d 04h	/t6507lp/trunk/rtl/verilog/
237	Added a preliminary collision detection logic.	creep	5660d 05h	/t6507lp/trunk/rtl/verilog/
236	Added the video converter testbench to the repository.	creep	5660d 08h	/t6507lp/trunk/rtl/verilog/
235	Bug #60: added a brief simulation to the video_converter module.	creep	5661d 02h	/t6507lp/trunk/rtl/verilog/
234	SBC Decimal mode 100% verified.	creep	5666d 04h	/t6507lp/trunk/rtl/verilog/
233	ADC and SBC are 100% verified in regular mode. Decimal mode still missing.	creep	5666d 08h	/t6507lp/trunk/rtl/verilog/
232	New video test.	creep	5668d 02h	/t6507lp/trunk/rtl/verilog/
231	Minor bugs fixed.	gabrieloshiro	5668d 03h	/t6507lp/trunk/rtl/verilog/
230	Changed TIA behavior. It is now pixel-based.	creep	5668d 03h	/t6507lp/trunk/rtl/verilog/
229	Created a one-line pattern.	creep	5668d 08h	/t6507lp/trunk/rtl/verilog/
228		gabrieloshiro	5668d 08h	/t6507lp/trunk/rtl/verilog/
227	Fixing conflicts.	creep	5668d 08h	/t6507lp/trunk/rtl/verilog/
226	work plz	creep	5668d 08h	/t6507lp/trunk/rtl/verilog/
225	Minor changes!	gabrieloshiro	5669d 01h	/t6507lp/trunk/rtl/verilog/
224	Added a top level for the tests.	creep	5669d 02h	/t6507lp/trunk/rtl/verilog/
223	Minor sintax errors fixed.	gabrieloshiro	5669d 03h	/t6507lp/trunk/rtl/verilog/

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 249

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