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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 42

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Rev Log message Author Age Path
38 root 5726d 15h /t6507lp/trunk/rtl/verilog/
37 Some minor fixes. Now we are trying to make it synthesizable. gabrieloshiro 5727d 12h /t6507lp/trunk/rtl/verilog/
36 All module names are written using uppercase letters now. gabrieloshiro 5727d 13h /t6507lp/trunk/rtl/verilog/
35 Several wires created to help code readibility. creep 5727d 13h /t6507lp/trunk/rtl/verilog/
34 Fixed state names. creep 5727d 15h /t6507lp/trunk/rtl/verilog/
33 Some portion of the absolute indexed mode is done, yet is fully nonfunctional. creep 5727d 15h /t6507lp/trunk/rtl/verilog/
32 Documentation is wrong. I`ve just kept the standard. Some ALU operations are not working 100%. Most of them don`t affect Processor Status Register yet. However the main body will be like this. :D gabrieloshiro 5727d 15h /t6507lp/trunk/rtl/verilog/
31 Added zero page indexed mode. creep 5727d 16h /t6507lp/trunk/rtl/verilog/
30 Added zero page mode. creep 5727d 16h /t6507lp/trunk/rtl/verilog/
29 Absolute addressing mode should be working. creep 5727d 17h /t6507lp/trunk/rtl/verilog/
28 More documentation. gabrieloshiro 5727d 18h /t6507lp/trunk/rtl/verilog/
27 Added the pipelining support for a few addressing modes. Still working on absolute addressing mode. creep 5727d 18h /t6507lp/trunk/rtl/verilog/
26 I`m still finishing the documentation. But the file should work by now. gabrieloshiro 5730d 12h /t6507lp/trunk/rtl/verilog/
25 Package file contains all important constants and local parameters. It assigns constant values for opcodes aliases, processor status register indexes, and addressing modes. It is going to help people to understand the code. T65 project has a lot of constants inside its codes. So it is hard to understand it. gabrieloshiro 5730d 13h /t6507lp/trunk/rtl/verilog/
24 Added some simple logic to a few states. Connection with the ALU is pending. creep 5730d 14h /t6507lp/trunk/rtl/verilog/
23 Updated file header standard. creep 5730d 15h /t6507lp/trunk/rtl/verilog/
22 Signal and module name convention. creep 5730d 15h /t6507lp/trunk/rtl/verilog/
21 *** empty log message *** creep 5730d 15h /t6507lp/trunk/rtl/verilog/
20 Added immediate, absolute and zero page addressing modes FSM branches. Five other modes still needed. Internal signal handling and temp registers still missing. creep 5730d 16h /t6507lp/trunk/rtl/verilog/
19 Parameters removed. creep 5730d 17h /t6507lp/trunk/rtl/verilog/

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