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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 56

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Rev Log message Author Age Path
56 Several changes in the output logic to respect the pipelining. creep 5604d 19h /t6507lp/trunk/rtl/verilog/
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5604d 20h /t6507lp/trunk/rtl/verilog/
54 Processor Status register modified. gabrieloshiro 5604d 23h /t6507lp/trunk/rtl/verilog/
53 Added default header. creep 5605d 03h /t6507lp/trunk/rtl/verilog/
52 Removed unecessary always block. creep 5605d 18h /t6507lp/trunk/rtl/verilog/
51 Some first ideas on testbench. creep 5605d 18h /t6507lp/trunk/rtl/verilog/
48 Updated reference to header file. creep 5605d 21h /t6507lp/trunk/rtl/verilog/
47 Added a new folder where the users should run the tools. creep 5605d 21h /t6507lp/trunk/rtl/verilog/
45 Removed the CVS $log tag. creep 5605d 21h /t6507lp/trunk/rtl/verilog/
44 Now it is compiling using ncvlog. creep 5605d 21h /t6507lp/trunk/rtl/verilog/
38 root 5606d 20h /t6507lp/trunk/rtl/verilog/
37 Some minor fixes. Now we are trying to make it synthesizable. gabrieloshiro 5607d 17h /t6507lp/trunk/rtl/verilog/
36 All module names are written using uppercase letters now. gabrieloshiro 5607d 18h /t6507lp/trunk/rtl/verilog/
35 Several wires created to help code readibility. creep 5607d 18h /t6507lp/trunk/rtl/verilog/
34 Fixed state names. creep 5607d 20h /t6507lp/trunk/rtl/verilog/
33 Some portion of the absolute indexed mode is done, yet is fully nonfunctional. creep 5607d 20h /t6507lp/trunk/rtl/verilog/
32 Documentation is wrong. I`ve just kept the standard. Some ALU operations are not working 100%. Most of them don`t affect Processor Status Register yet. However the main body will be like this. :D gabrieloshiro 5607d 20h /t6507lp/trunk/rtl/verilog/
31 Added zero page indexed mode. creep 5607d 21h /t6507lp/trunk/rtl/verilog/
30 Added zero page mode. creep 5607d 21h /t6507lp/trunk/rtl/verilog/
29 Absolute addressing mode should be working. creep 5607d 22h /t6507lp/trunk/rtl/verilog/

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