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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 67

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Rev Log message Author Age Path
67 File name change to lowercase. HAL says so! creep 5626d 16h /t6507lp/trunk/rtl/verilog/
66 File name change to lowercase. HAL says so! creep 5626d 16h /t6507lp/trunk/rtl/verilog/
65 Now the blocks are connected. gabrieloshiro 5627d 11h /t6507lp/trunk/rtl/verilog/
64 Constant were wrong. gabrieloshiro 5627d 11h /t6507lp/trunk/rtl/verilog/
63 Fixed several HAL warnings. Still plenty to do. creep 5627d 11h /t6507lp/trunk/rtl/verilog/
62 The DUT file name changed. creep 5627d 11h /t6507lp/trunk/rtl/verilog/
61 File name change to lowercase. HAL says so! creep 5627d 12h /t6507lp/trunk/rtl/verilog/
60 File name change. HAL says so! creep 5627d 12h /t6507lp/trunk/rtl/verilog/
59 I`ve fixed some latch creation. gabrieloshiro 5627d 12h /t6507lp/trunk/rtl/verilog/
58 ALU with all opcodes ready for simulation. gabrieloshiro 5627d 13h /t6507lp/trunk/rtl/verilog/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5627d 13h /t6507lp/trunk/rtl/verilog/
56 Several changes in the output logic to respect the pipelining. creep 5627d 13h /t6507lp/trunk/rtl/verilog/
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5627d 14h /t6507lp/trunk/rtl/verilog/
54 Processor Status register modified. gabrieloshiro 5627d 17h /t6507lp/trunk/rtl/verilog/
53 Added default header. creep 5627d 21h /t6507lp/trunk/rtl/verilog/
52 Removed unecessary always block. creep 5628d 12h /t6507lp/trunk/rtl/verilog/
51 Some first ideas on testbench. creep 5628d 12h /t6507lp/trunk/rtl/verilog/
48 Updated reference to header file. creep 5628d 15h /t6507lp/trunk/rtl/verilog/
47 Added a new folder where the users should run the tools. creep 5628d 15h /t6507lp/trunk/rtl/verilog/
45 Removed the CVS $log tag. creep 5628d 15h /t6507lp/trunk/rtl/verilog/

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