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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 70

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Rev Log message Author Age Path
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5604d 14h /t6507lp/trunk/rtl/verilog/
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5604d 16h /t6507lp/trunk/rtl/verilog/
67 File name change to lowercase. HAL says so! creep 5604d 18h /t6507lp/trunk/rtl/verilog/
66 File name change to lowercase. HAL says so! creep 5604d 18h /t6507lp/trunk/rtl/verilog/
65 Now the blocks are connected. gabrieloshiro 5605d 13h /t6507lp/trunk/rtl/verilog/
64 Constant were wrong. gabrieloshiro 5605d 13h /t6507lp/trunk/rtl/verilog/
63 Fixed several HAL warnings. Still plenty to do. creep 5605d 13h /t6507lp/trunk/rtl/verilog/
62 The DUT file name changed. creep 5605d 13h /t6507lp/trunk/rtl/verilog/
61 File name change to lowercase. HAL says so! creep 5605d 14h /t6507lp/trunk/rtl/verilog/
60 File name change. HAL says so! creep 5605d 14h /t6507lp/trunk/rtl/verilog/
59 I`ve fixed some latch creation. gabrieloshiro 5605d 14h /t6507lp/trunk/rtl/verilog/
58 ALU with all opcodes ready for simulation. gabrieloshiro 5605d 15h /t6507lp/trunk/rtl/verilog/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5605d 15h /t6507lp/trunk/rtl/verilog/
56 Several changes in the output logic to respect the pipelining. creep 5605d 15h /t6507lp/trunk/rtl/verilog/
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5605d 16h /t6507lp/trunk/rtl/verilog/
54 Processor Status register modified. gabrieloshiro 5605d 18h /t6507lp/trunk/rtl/verilog/
53 Added default header. creep 5605d 23h /t6507lp/trunk/rtl/verilog/
52 Removed unecessary always block. creep 5606d 14h /t6507lp/trunk/rtl/verilog/
51 Some first ideas on testbench. creep 5606d 14h /t6507lp/trunk/rtl/verilog/
48 Updated reference to header file. creep 5606d 16h /t6507lp/trunk/rtl/verilog/

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