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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 79

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Rev Log message Author Age Path
79 ALU testbench added. gabrieloshiro 5630d 12h /t6507lp/trunk/rtl/verilog/
78 ZPG coded and simulated. creep 5630d 12h /t6507lp/trunk/rtl/verilog/
77 ZPG coded. Simulation is halfway. creep 5630d 13h /t6507lp/trunk/rtl/verilog/
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5630d 13h /t6507lp/trunk/rtl/verilog/
75 First working version! gabrieloshiro 5630d 13h /t6507lp/trunk/rtl/verilog/
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5630d 13h /t6507lp/trunk/rtl/verilog/
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5634d 10h /t6507lp/trunk/rtl/verilog/
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5634d 12h /t6507lp/trunk/rtl/verilog/
67 File name change to lowercase. HAL says so! creep 5634d 14h /t6507lp/trunk/rtl/verilog/
66 File name change to lowercase. HAL says so! creep 5634d 14h /t6507lp/trunk/rtl/verilog/
65 Now the blocks are connected. gabrieloshiro 5635d 09h /t6507lp/trunk/rtl/verilog/
64 Constant were wrong. gabrieloshiro 5635d 09h /t6507lp/trunk/rtl/verilog/
63 Fixed several HAL warnings. Still plenty to do. creep 5635d 09h /t6507lp/trunk/rtl/verilog/
62 The DUT file name changed. creep 5635d 09h /t6507lp/trunk/rtl/verilog/
61 File name change to lowercase. HAL says so! creep 5635d 10h /t6507lp/trunk/rtl/verilog/
60 File name change. HAL says so! creep 5635d 10h /t6507lp/trunk/rtl/verilog/
59 I`ve fixed some latch creation. gabrieloshiro 5635d 10h /t6507lp/trunk/rtl/verilog/
58 ALU with all opcodes ready for simulation. gabrieloshiro 5635d 10h /t6507lp/trunk/rtl/verilog/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5635d 11h /t6507lp/trunk/rtl/verilog/
56 Several changes in the output logic to respect the pipelining. creep 5635d 11h /t6507lp/trunk/rtl/verilog/

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