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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 87

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Rev Log message Author Age Path
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5605d 18h /t6507lp/trunk/rtl/verilog/
86 Zero page indexed mode is working fine. creep 5605d 22h /t6507lp/trunk/rtl/verilog/
85 alu_x and alu_y variables created. gabrieloshiro 5606d 02h /t6507lp/trunk/rtl/verilog/
84 X and Y register are passed from ALU to FSM. gabrieloshiro 5606d 02h /t6507lp/trunk/rtl/verilog/
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5606d 03h /t6507lp/trunk/rtl/verilog/
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5606d 19h /t6507lp/trunk/rtl/verilog/
81 Decimal mode (BCD) is working. gabrieloshiro 5606d 19h /t6507lp/trunk/rtl/verilog/
80 Grouping some instructions that have the same behavioral. gabrieloshiro 5606d 20h /t6507lp/trunk/rtl/verilog/
79 ALU testbench added. gabrieloshiro 5606d 21h /t6507lp/trunk/rtl/verilog/
78 ZPG coded and simulated. creep 5606d 21h /t6507lp/trunk/rtl/verilog/
77 ZPG coded. Simulation is halfway. creep 5606d 22h /t6507lp/trunk/rtl/verilog/
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5606d 22h /t6507lp/trunk/rtl/verilog/
75 First working version! gabrieloshiro 5606d 22h /t6507lp/trunk/rtl/verilog/
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5606d 22h /t6507lp/trunk/rtl/verilog/
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5610d 19h /t6507lp/trunk/rtl/verilog/
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5610d 21h /t6507lp/trunk/rtl/verilog/
67 File name change to lowercase. HAL says so! creep 5610d 23h /t6507lp/trunk/rtl/verilog/
66 File name change to lowercase. HAL says so! creep 5610d 23h /t6507lp/trunk/rtl/verilog/
65 Now the blocks are connected. gabrieloshiro 5611d 18h /t6507lp/trunk/rtl/verilog/
64 Constant were wrong. gabrieloshiro 5611d 18h /t6507lp/trunk/rtl/verilog/

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