URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] [vhdl/] - Rev 41

Rev	Log message	Author	Age	Path
41	Removed UNISIM library	jesus	7900d 05h	/t80/trunk/rtl/vhdl/
40	Cleanup	jesus	7900d 05h	/t80/trunk/rtl/vhdl/
37	Changed to single register file	jesus	7928d 05h	/t80/trunk/rtl/vhdl/
36	Added component declaration	jesus	7928d 05h	/t80/trunk/rtl/vhdl/
35	Release 0242	jesus	7934d 17h	/t80/trunk/rtl/vhdl/
34	Updated for ISE 5.1	jesus	7934d 22h	/t80/trunk/rtl/vhdl/
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7953d 16h	/t80/trunk/rtl/vhdl/
27	Xilinx SSRAM, initial release	jesus	7954d 16h	/t80/trunk/rtl/vhdl/
26	Fixed instruction timing for POP and DJNZ	jesus	7968d 08h	/t80/trunk/rtl/vhdl/
25	IX/IY timing and ADC/SBC fix	jesus	7969d 18h	/t80/trunk/rtl/vhdl/
24	no message	jesus	7975d 15h	/t80/trunk/rtl/vhdl/
23	Fixed T2Write	jesus	7975d 15h	/t80/trunk/rtl/vhdl/
22	Added 8080 top level	jesus	7975d 15h	/t80/trunk/rtl/vhdl/
20	Updated for new T80s generic	jesus	7980d 14h	/t80/trunk/rtl/vhdl/
19	Initial version	jesus	7980d 14h	/t80/trunk/rtl/vhdl/
18	Added T2Write generic	jesus	7980d 21h	/t80/trunk/rtl/vhdl/
17	Removed write through	jesus	7982d 13h	/t80/trunk/rtl/vhdl/
16	no message	jesus	7982d 17h	/t80/trunk/rtl/vhdl/
15	Added clock enable and fixed IM 2	jesus	7989d 16h	/t80/trunk/rtl/vhdl/
12	Initial import	jesus	8009d 04h	/t80/trunk/rtl/vhdl/