URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] [vhdl/] - Rev 47

Rev	Log message	Author	Age	Path
47	New directory structure.	root	5555d 11h	/t80/trunk/rtl/vhdl/
46	Made some bugfixes	andreas	6843d 04h	/t80/trunk/rtl/vhdl/
45	Fixed loopback break generation	jesus	7844d 06h	/t80/trunk/rtl/vhdl/
44	Added some missing features and fixed baud rate generator	jesus	7844d 19h	/t80/trunk/rtl/vhdl/
42	Fixed bus req/ack cycle	jesus	7853d 07h	/t80/trunk/rtl/vhdl/
41	Removed UNISIM library	jesus	7853d 07h	/t80/trunk/rtl/vhdl/
40	Cleanup	jesus	7853d 07h	/t80/trunk/rtl/vhdl/
37	Changed to single register file	jesus	7881d 07h	/t80/trunk/rtl/vhdl/
36	Added component declaration	jesus	7881d 07h	/t80/trunk/rtl/vhdl/
35	Release 0242	jesus	7887d 19h	/t80/trunk/rtl/vhdl/
34	Updated for ISE 5.1	jesus	7888d 01h	/t80/trunk/rtl/vhdl/
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7906d 18h	/t80/trunk/rtl/vhdl/
27	Xilinx SSRAM, initial release	jesus	7907d 18h	/t80/trunk/rtl/vhdl/
26	Fixed instruction timing for POP and DJNZ	jesus	7921d 10h	/t80/trunk/rtl/vhdl/
25	IX/IY timing and ADC/SBC fix	jesus	7922d 20h	/t80/trunk/rtl/vhdl/
24	no message	jesus	7928d 17h	/t80/trunk/rtl/vhdl/
23	Fixed T2Write	jesus	7928d 17h	/t80/trunk/rtl/vhdl/
22	Added 8080 top level	jesus	7928d 17h	/t80/trunk/rtl/vhdl/
20	Updated for new T80s generic	jesus	7933d 16h	/t80/trunk/rtl/vhdl/
19	Initial version	jesus	7933d 16h	/t80/trunk/rtl/vhdl/