| Rev |
Log message |
Author |
Age |
Path |
| 32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4397d 08h |
/tinycpu/ |
| 31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4398d 04h |
/tinycpu/ |
| 30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4398d 04h |
/tinycpu/ |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4401d 11h |
/tinycpu/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4402d 06h |
/tinycpu/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4402d 12h |
/tinycpu/ |
| 26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4402d 13h |
/tinycpu/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4402d 17h |
/tinycpu/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4403d 10h |
/tinycpu/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4403d 11h |
/tinycpu/ |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4404d 02h |
/tinycpu/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4404d 03h |
/tinycpu/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4405d 02h |
/tinycpu/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4405d 04h |
/tinycpu/ |
| 18 |
Finished memory controller |
earlz |
4408d 14h |
/tinycpu/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4409d 03h |
/tinycpu/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4412d 06h |
/tinycpu/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4414d 03h |
/tinycpu/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4414d 11h |
/tinycpu/ |
| 13 |
Forgot about the new library I added |
earlz |
4414d 14h |
/tinycpu/ |
