| Rev |
Log message |
Author |
Age |
Path |
| 38 |
Made it synthesize without latches |
earlz |
4402d 20h |
/tinycpu/trunk/src/ |
| 37 |
Worked on the assembler more
Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some |
earlz |
4404d 18h |
/tinycpu/trunk/src/ |
| 34 |
Implemented load and store instructions (`mov reg, [reg]` and `mov [reg], reg` respectively) |
earlz |
4405d 18h |
/tinycpu/trunk/src/ |
| 33 |
Added more test cases for push/pop. More are still needed though
Fixed SP increment/decrementing
Added new opcode `mov reg,reg` so debugging isn't such a pain |
earlz |
4405d 22h |
/tinycpu/trunk/src/ |
| 32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4405d 23h |
/tinycpu/trunk/src/ |
| 31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4406d 18h |
/tinycpu/trunk/src/ |
| 30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4406d 19h |
/tinycpu/trunk/src/ |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4410d 02h |
/tinycpu/trunk/src/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4410d 20h |
/tinycpu/trunk/src/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4411d 02h |
/tinycpu/trunk/src/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4411d 07h |
/tinycpu/trunk/src/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4412d 01h |
/tinycpu/trunk/src/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4412d 01h |
/tinycpu/trunk/src/ |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4412d 17h |
/tinycpu/trunk/src/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4412d 17h |
/tinycpu/trunk/src/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4413d 17h |
/tinycpu/trunk/src/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4413d 19h |
/tinycpu/trunk/src/ |
| 18 |
Finished memory controller |
earlz |
4417d 04h |
/tinycpu/trunk/src/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4417d 18h |
/tinycpu/trunk/src/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4420d 20h |
/tinycpu/trunk/src/ |
