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[/] [tinycpu/] [trunk/] [testbench/] - Rev 20

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20 fuck it. All sorts of broken, will try to fix it tomorrow earlz 4456d 14h /tinycpu/trunk/testbench/
19 Got beginning of core/decoder for the CPU earlz 4456d 16h /tinycpu/trunk/testbench/
18 Finished memory controller earlz 4460d 01h /tinycpu/trunk/testbench/
17 Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct		 earlz 4460d 15h /tinycpu/trunk/testbench/
16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.		 earlz 4463d 17h /tinycpu/trunk/testbench/
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4465d 15h /tinycpu/trunk/testbench/
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4465d 23h /tinycpu/trunk/testbench/
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD		 earlz 4466d 02h /tinycpu/trunk/testbench/
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4469d 15h /tinycpu/trunk/testbench/
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4469d 16h /tinycpu/trunk/testbench/
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4470d 00h /tinycpu/trunk/testbench/
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing		 earlz 4470d 23h /tinycpu/trunk/testbench/
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)		 earlz 4471d 00h /tinycpu/trunk/testbench/
5 Modified registerfile to be dual-port for both read and write earlz 4471d 16h /tinycpu/trunk/testbench/
4 Added internal memory interface
Updated design		 earlz 4472d 00h /tinycpu/trunk/testbench/
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming		 earlz 4472d 16h /tinycpu/trunk/testbench/
2 Initial commit earlz 4472d 17h /tinycpu/trunk/testbench/

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