| Rev |
Log message |
Author |
Age |
Path |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4399d 04h |
/tinycpu/trunk/testbench/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4399d 10h |
/tinycpu/trunk/testbench/ |
| 26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4399d 11h |
/tinycpu/trunk/testbench/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4399d 15h |
/tinycpu/trunk/testbench/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4400d 08h |
/tinycpu/trunk/testbench/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4400d 09h |
/tinycpu/trunk/testbench/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4401d 01h |
/tinycpu/trunk/testbench/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4402d 01h |
/tinycpu/trunk/testbench/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4402d 02h |
/tinycpu/trunk/testbench/ |
| 18 |
Finished memory controller |
earlz |
4405d 12h |
/tinycpu/trunk/testbench/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4406d 01h |
/tinycpu/trunk/testbench/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4409d 04h |
/tinycpu/trunk/testbench/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4411d 01h |
/tinycpu/trunk/testbench/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4411d 09h |
/tinycpu/trunk/testbench/ |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4411d 13h |
/tinycpu/trunk/testbench/ |
| 11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4415d 02h |
/tinycpu/trunk/testbench/ |
| 10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4415d 02h |
/tinycpu/trunk/testbench/ |
| 9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4415d 10h |
/tinycpu/trunk/testbench/ |
| 8 |
Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing |
earlz |
4416d 10h |
/tinycpu/trunk/testbench/ |
| 7 |
Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000) |
earlz |
4416d 11h |
/tinycpu/trunk/testbench/ |
