| Rev |
Log message |
Author |
Age |
Path |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4413d 14h |
/tinycpu/trunk/testbench/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4414d 08h |
/tinycpu/trunk/testbench/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4414d 14h |
/tinycpu/trunk/testbench/ |
| 26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4414d 16h |
/tinycpu/trunk/testbench/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4414d 20h |
/tinycpu/trunk/testbench/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4415d 13h |
/tinycpu/trunk/testbench/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4415d 14h |
/tinycpu/trunk/testbench/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4416d 06h |
/tinycpu/trunk/testbench/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4417d 05h |
/tinycpu/trunk/testbench/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4417d 07h |
/tinycpu/trunk/testbench/ |
| 18 |
Finished memory controller |
earlz |
4420d 17h |
/tinycpu/trunk/testbench/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4421d 06h |
/tinycpu/trunk/testbench/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4424d 09h |
/tinycpu/trunk/testbench/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4426d 06h |
/tinycpu/trunk/testbench/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4426d 14h |
/tinycpu/trunk/testbench/ |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4426d 17h |
/tinycpu/trunk/testbench/ |
| 11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4430d 07h |
/tinycpu/trunk/testbench/ |
| 10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4430d 07h |
/tinycpu/trunk/testbench/ |
| 9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4430d 15h |
/tinycpu/trunk/testbench/ |
| 8 |
Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing |
earlz |
4431d 14h |
/tinycpu/trunk/testbench/ |
