Rev |
Log message |
Author |
Age |
Path |
39 |
A lot of work in the assembler. It now supports nearly every opcode implemented and is a lot cleaner
Added a bootrom. There isn't really a point in testbenching this.. I'm not for sure how I would, and it will change so much in these early days that it'll be pointless I think
Everything should be ready to go for a test on actual hardware now! |
earlz |
4403d 05h |
/tinycpu/trunk/testbench/ |
37 |
Worked on the assembler more
Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some |
earlz |
4405d 05h |
/tinycpu/trunk/testbench/ |
34 |
Implemented load and store instructions (`mov reg, [reg]` and `mov [reg], reg` respectively) |
earlz |
4406d 06h |
/tinycpu/trunk/testbench/ |
33 |
Added more test cases for push/pop. More are still needed though
Fixed SP increment/decrementing
Added new opcode `mov reg,reg` so debugging isn't such a pain |
earlz |
4406d 10h |
/tinycpu/trunk/testbench/ |
32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4406d 11h |
/tinycpu/trunk/testbench/ |
31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4407d 06h |
/tinycpu/trunk/testbench/ |
30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4407d 07h |
/tinycpu/trunk/testbench/ |
29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4410d 13h |
/tinycpu/trunk/testbench/ |
28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4411d 08h |
/tinycpu/trunk/testbench/ |
27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4411d 14h |
/tinycpu/trunk/testbench/ |
26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4411d 15h |
/tinycpu/trunk/testbench/ |
25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4411d 19h |
/tinycpu/trunk/testbench/ |
24 |
Good news, mov to IP actually works as expected! |
earlz |
4412d 13h |
/tinycpu/trunk/testbench/ |
23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4412d 13h |
/tinycpu/trunk/testbench/ |
21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4413d 05h |
/tinycpu/trunk/testbench/ |
20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4414d 05h |
/tinycpu/trunk/testbench/ |
19 |
Got beginning of core/decoder for the CPU |
earlz |
4414d 06h |
/tinycpu/trunk/testbench/ |
18 |
Finished memory controller |
earlz |
4417d 16h |
/tinycpu/trunk/testbench/ |
17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4418d 06h |
/tinycpu/trunk/testbench/ |
16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4421d 08h |
/tinycpu/trunk/testbench/ |