URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] - Rev 97

Rev	Log message	Author	Age	Path
97	Added data in mux, added 16450 UART to environment	ghutchis	5305d 04h	/tv80/
96	Added Z80 op decode to environment, enabled by -k switch	ghutchis	5305d 09h	/tv80/
95	Updated regression script to use SystemC simulation	ghutchis	5307d 05h	/tv80/
94	Ported over env_io.v from Verilog environment to tv_responder. Basic tests from Verilog environment (hello, fib) now passing in SystemC environment.	ghutchis	5309d 05h	/tv80/
93	Added common header file for all systemc environment	ghutchis	5310d 04h	/tv80/
92	Added responder to top level, beginning of support for ihex load	ghutchis	5314d 05h	/tv80/
91	Preliminary support for SystemC/Verilator environment	ghutchis	5314d 08h	/tv80/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5314d 08h	/tv80/
89	RTL and environment fixes for nmi bug	ghutchis	5334d 11h	/tv80/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5336d 01h	/tv80/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5351d 09h	/tv80/
86	Added old uploaded documents to new repository.	root	5574d 15h	/tv80/
85	Added old uploaded documents to new repository.	root	5574d 21h	/tv80/
84	New directory structure.	root	5574d 21h	/tv80/