URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [tags/] [rel_1_0/] [env/] - Rev 108

Rev	Log message	Author	Age	Path
84	New directory structure.	root	5673d 12h	/tv80/tags/rel_1_0/env/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		7010d 05h	/tv80/tags/rel_1_0/env/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	7010d 05h	/tv80/tags/rel_1_0/env/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7133d 23h	/tv80/tags/rel_1_0/env/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7142d 00h	/tv80/tags/rel_1_0/env/
56	Updated env for simple_gmii with async clk	ghutchis	7216d 22h	/tv80/tags/rel_1_0/env/
53	Added environment hooks for using and testing the GMII interface	ghutchis	7218d 21h	/tv80/tags/rel_1_0/env/
42	Added decode of OUT (##),A instruction Removed dump-by-default and added DUMP_START define	ghutchis	7256d 16h	/tv80/tags/rel_1_0/env/
41	Added random-read value port	ghutchis	7258d 20h	/tv80/tags/rel_1_0/env/
37	Added new I/O registers for testing block I/O	ghutchis	7260d 14h	/tv80/tags/rel_1_0/env/
36	Removed default instruction decode	ghutchis	7260d 14h	/tv80/tags/rel_1_0/env/
31	1) Added environment support for Z80 op decode in log file. 2) Fixed env support for interrupt generation and clearing	ghutchis	7277d 01h	/tv80/tags/rel_1_0/env/
28	Added code to initialize RAM to all 00 at environment start-up time.	ghutchis	7280d 00h	/tv80/tags/rel_1_0/env/
2	Initial commit	ghutchis	7432d 05h	/tv80/tags/rel_1_0/env/