URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [tags/] [rel_1_0/] [rtl/] - Rev 65

Rev	Log message	Author	Age	Path
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7124d 17h	/tv80/tags/rel_1_0/rtl/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7159d 20h	/tv80/tags/rel_1_0/rtl/
58	Made TX path async Made TX clock input instead of output	ghutchis	7199d 08h	/tv80/tags/rel_1_0/rtl/
52	Added simple GMII-like interface for testing	ghutchis	7201d 14h	/tv80/tags/rel_1_0/rtl/
45	Added negedge version of top	ghutchis	7216d 17h	/tv80/tags/rel_1_0/rtl/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7244d 15h	/tv80/tags/rel_1_0/rtl/
24	tv80s.v	ghutchis	7273d 07h	/tv80/tags/rel_1_0/rtl/
23	Completed conversion to one-hot encoding	ghutchis	7285d 21h	/tv80/tags/rel_1_0/rtl/
22	Changed starting state for one-hot tstate	ghutchis	7285d 21h	/tv80/tags/rel_1_0/rtl/
21	Replaced encoded states with one-hot	ghutchis	7286d 22h	/tv80/tags/rel_1_0/rtl/
4	Removed obsolete top level	ghutchis	7414d 19h	/tv80/tags/rel_1_0/rtl/
2	Initial commit	ghutchis	7414d 22h	/tv80/tags/rel_1_0/rtl/