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[/] [tv80/] [tags/] [rel_1_0/] [rtl/] - Rev 76

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76 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6933d 19h /tv80/tags/rel_1_0/rtl/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6933d 20h /tv80/tags/rel_1_0/rtl/
71 Ported UART from T80 ghutchis 7006d 19h /tv80/tags/rel_1_0/rtl/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic		 ghutchis 7065d 15h /tv80/tags/rel_1_0/rtl/
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.		 ghutchis 7100d 18h /tv80/tags/rel_1_0/rtl/
58 Made TX path async
Made TX clock input instead of output		 ghutchis 7140d 05h /tv80/tags/rel_1_0/rtl/
52 Added simple GMII-like interface for testing ghutchis 7142d 12h /tv80/tags/rel_1_0/rtl/
45 Added negedge version of top ghutchis 7157d 15h /tv80/tags/rel_1_0/rtl/
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7185d 13h /tv80/tags/rel_1_0/rtl/
24 tv80s.v ghutchis 7214d 05h /tv80/tags/rel_1_0/rtl/
23 Completed conversion to one-hot encoding ghutchis 7226d 19h /tv80/tags/rel_1_0/rtl/
22 Changed starting state for one-hot tstate ghutchis 7226d 19h /tv80/tags/rel_1_0/rtl/
21 Replaced encoded states with one-hot ghutchis 7227d 19h /tv80/tags/rel_1_0/rtl/
4 Removed obsolete top level ghutchis 7355d 16h /tv80/tags/rel_1_0/rtl/
2 Initial commit ghutchis 7355d 19h /tv80/tags/rel_1_0/rtl/

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