OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 88

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5325d 05h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5340d 12h /tv80/trunk/
84 New directory structure. root 5564d 00h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5637d 06h /trunk/
82 Clean up spacing hharte 5647d 02h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5647d 02h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6746d 15h /trunk/
79 Added JR self-checking test ghutchis 6746d 15h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6789d 16h /trunk/
77 Added back files lost after server crash ghutchis 6821d 10h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6900d 16h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6900d 17h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6912d 12h /trunk/
72 Added copyright header ghutchis 6912d 12h /trunk/
71 Ported UART from T80 ghutchis 6973d 16h /trunk/
70 Added test for T16450 UART ghutchis 7024d 11h /trunk/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7024d 11h /trunk/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7032d 11h /trunk/
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.		 ghutchis 7032d 11h /trunk/
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7032d 12h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.