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[/] [tv80/] [trunk/] - Rev 89

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Rev Log message Author Age Path
89 RTL and environment fixes for nmi bug ghutchis 5376d 21h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5378d 11h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5393d 19h /tv80/trunk/
84 New directory structure. root 5617d 07h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5690d 13h /trunk/
82 Clean up spacing hharte 5700d 09h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5700d 09h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6799d 22h /trunk/
79 Added JR self-checking test ghutchis 6799d 22h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6842d 23h /trunk/
77 Added back files lost after server crash ghutchis 6874d 17h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6953d 23h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6954d 00h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6965d 19h /trunk/
72 Added copyright header ghutchis 6965d 19h /trunk/
71 Ported UART from T80 ghutchis 7026d 23h /trunk/
70 Added test for T16450 UART ghutchis 7077d 18h /trunk/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7077d 18h /trunk/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7085d 18h /trunk/
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.		 ghutchis 7085d 18h /trunk/

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