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[/] [tv80/] [trunk/] - Rev 90

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Rev Log message Author Age Path
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5357d 19h /tv80/trunk/
89 RTL and environment fixes for nmi bug ghutchis 5377d 22h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5379d 13h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5394d 20h /tv80/trunk/
84 New directory structure. root 5618d 08h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5691d 14h /trunk/
82 Clean up spacing hharte 5701d 11h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5701d 11h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6800d 23h /trunk/
79 Added JR self-checking test ghutchis 6800d 23h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6844d 01h /trunk/
77 Added back files lost after server crash ghutchis 6875d 19h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6955d 01h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6955d 02h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6966d 21h /trunk/
72 Added copyright header ghutchis 6966d 21h /trunk/
71 Ported UART from T80 ghutchis 7028d 00h /trunk/
70 Added test for T16450 UART ghutchis 7078d 19h /trunk/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7078d 19h /trunk/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7086d 20h /trunk/

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