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[/] [tv80/] [trunk/] - Rev 90

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Rev Log message Author Age Path
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5303d 12h /tv80/trunk/
89 RTL and environment fixes for nmi bug ghutchis 5323d 15h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5325d 05h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5340d 13h /tv80/trunk/
84 New directory structure. root 5564d 01h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5637d 07h /trunk/
82 Clean up spacing hharte 5647d 03h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5647d 03h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6746d 16h /trunk/
79 Added JR self-checking test ghutchis 6746d 16h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6789d 17h /trunk/
77 Added back files lost after server crash ghutchis 6821d 11h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6900d 17h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6900d 18h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6912d 13h /trunk/
72 Added copyright header ghutchis 6912d 13h /trunk/
71 Ported UART from T80 ghutchis 6973d 17h /trunk/
70 Added test for T16450 UART ghutchis 7024d 12h /trunk/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7024d 12h /trunk/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7032d 12h /trunk/

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