URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 91

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Rev	Log message	Author	Age	Path
91	Preliminary support for SystemC/Verilator environment	ghutchis	5312d 14h	/tv80/trunk/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5312d 14h	/tv80/trunk/
89	RTL and environment fixes for nmi bug	ghutchis	5332d 17h	/tv80/trunk/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5334d 08h	/tv80/trunk/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5349d 15h	/tv80/trunk/
84	New directory structure.	root	5573d 03h	/tv80/trunk/
83	Some fixes from Guy-- replace case with casex.	hharte	5646d 09h	/trunk/
82	Clean up spacing	hharte	5656d 05h	/trunk/
81	Initial version of TV80 Wishbone Wrapper	hharte	5656d 06h	/trunk/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6755d 18h	/trunk/
79	Added JR self-checking test	ghutchis	6755d 18h	/trunk/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6798d 19h	/trunk/
77	Added back files lost after server crash	ghutchis	6830d 13h	/trunk/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6909d 19h	/trunk/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6909d 21h	/trunk/
73	Added RC4 encrypt/decrypt test	ghutchis	6921d 15h	/trunk/
72	Added copyright header	ghutchis	6921d 15h	/trunk/
71	Ported UART from T80	ghutchis	6982d 19h	/trunk/
70	Added test for T16450 UART	ghutchis	7033d 14h	/trunk/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7033d 14h	/trunk/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 91

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