URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 91

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Rev	Log message	Author	Age	Path
91	Preliminary support for SystemC/Verilator environment	ghutchis	5356d 18h	/tv80/trunk/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5356d 18h	/tv80/trunk/
89	RTL and environment fixes for nmi bug	ghutchis	5376d 21h	/tv80/trunk/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5378d 12h	/tv80/trunk/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5393d 20h	/tv80/trunk/
84	New directory structure.	root	5617d 07h	/tv80/trunk/
83	Some fixes from Guy-- replace case with casex.	hharte	5690d 14h	/trunk/
82	Clean up spacing	hharte	5700d 10h	/trunk/
81	Initial version of TV80 Wishbone Wrapper	hharte	5700d 10h	/trunk/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6799d 22h	/trunk/
79	Added JR self-checking test	ghutchis	6799d 22h	/trunk/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6843d 00h	/trunk/
77	Added back files lost after server crash	ghutchis	6874d 18h	/trunk/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6954d 00h	/trunk/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6954d 01h	/trunk/
73	Added RC4 encrypt/decrypt test	ghutchis	6965d 20h	/trunk/
72	Added copyright header	ghutchis	6965d 20h	/trunk/
71	Ported UART from T80	ghutchis	7026d 23h	/trunk/
70	Added test for T16450 UART	ghutchis	7077d 18h	/trunk/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7077d 18h	/trunk/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 91

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