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[/] [tv80/] [trunk/] - Rev 95

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Rev Log message Author Age Path
95 Updated regression script to use SystemC simulation ghutchis 5328d 14h /tv80/trunk/
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.		 ghutchis 5330d 15h /tv80/trunk/
93 Added common header file for all systemc environment ghutchis 5331d 13h /tv80/trunk/
92 Added responder to top level, beginning of support for ihex load ghutchis 5335d 14h /tv80/trunk/
91 Preliminary support for SystemC/Verilator environment ghutchis 5335d 17h /tv80/trunk/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5335d 17h /tv80/trunk/
89 RTL and environment fixes for nmi bug ghutchis 5355d 20h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5357d 10h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5372d 18h /tv80/trunk/
84 New directory structure. root 5596d 06h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5669d 12h /trunk/
82 Clean up spacing hharte 5679d 08h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5679d 08h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6778d 21h /trunk/
79 Added JR self-checking test ghutchis 6778d 21h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6821d 22h /trunk/
77 Added back files lost after server crash ghutchis 6853d 16h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6932d 22h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6932d 23h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6944d 18h /trunk/

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