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[/] [tv80/] [trunk/] - Rev 95

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Rev Log message Author Age Path
95 Updated regression script to use SystemC simulation ghutchis 5296d 07h /tv80/trunk/
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.		 ghutchis 5298d 08h /tv80/trunk/
93 Added common header file for all systemc environment ghutchis 5299d 07h /tv80/trunk/
92 Added responder to top level, beginning of support for ihex load ghutchis 5303d 08h /tv80/trunk/
91 Preliminary support for SystemC/Verilator environment ghutchis 5303d 10h /tv80/trunk/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5303d 10h /tv80/trunk/
89 RTL and environment fixes for nmi bug ghutchis 5323d 13h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5325d 04h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5340d 12h /tv80/trunk/
84 New directory structure. root 5563d 23h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5637d 06h /trunk/
82 Clean up spacing hharte 5647d 02h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5647d 02h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6746d 14h /trunk/
79 Added JR self-checking test ghutchis 6746d 14h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6789d 16h /trunk/
77 Added back files lost after server crash ghutchis 6821d 10h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6900d 16h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6900d 17h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6912d 12h /trunk/

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