URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [env/] - Rev 92

Rev	Log message	Author	Age	Path
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5311d 19h	/tv80/trunk/env/
89	RTL and environment fixes for nmi bug	ghutchis	5331d 22h	/tv80/trunk/env/
84	New directory structure.	root	5572d 08h	/tv80/trunk/env/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6909d 00h	/trunk/env/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7032d 19h	/trunk/env/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7040d 20h	/trunk/env/
56	Updated env for simple_gmii with async clk	ghutchis	7115d 17h	/trunk/env/
53	Added environment hooks for using and testing the GMII interface	ghutchis	7117d 17h	/trunk/env/
42	Added decode of OUT (##),A instruction Removed dump-by-default and added DUMP_START define	ghutchis	7155d 12h	/trunk/env/
41	Added random-read value port	ghutchis	7157d 16h	/trunk/env/
37	Added new I/O registers for testing block I/O	ghutchis	7159d 09h	/trunk/env/
36	Removed default instruction decode	ghutchis	7159d 10h	/trunk/env/
31	1) Added environment support for Z80 op decode in log file. 2) Fixed env support for interrupt generation and clearing	ghutchis	7175d 20h	/trunk/env/
28	Added code to initialize RAM to all 00 at environment start-up time.	ghutchis	7178d 20h	/trunk/env/
2	Initial commit	ghutchis	7331d 00h	/trunk/env/